As it is known in the art, a plurality of integrated circuits are generally fabricated on a common wafer and cut i.e. diced into individual integrated circuit chips or dies. Some or all of these integrated circuits are generally tested to ensure that the integrated circuits function as anticipated. One common way of ensuring that an integrated circuit chip operates as expected is through the use of a chip tester apparatus.
The chip tester apparatus when used to test packaged integrated circuit chips, for example, includes a socket having a plurality of hollow pins to hold and electrically connect to pins of a packaged integrated circuit under test. Generally the pin positions of the socket correspond to respective input and output terminals of the integrated circuit. The chip tester apparatus also includes a Read Only Memory (ROM) device used to store a set of test vectors which are fed to the integrated circuit under test. Each test vector includes a given number of binary bits elements, and each bit corresponds to a pin on the respective integrated circuit. For example, a test vector which is used to test a 16 pin integrated circuit would include 16 binary bits.
For the bits which correspond to the input terminals of the integrated circuit, the value of the bit is representative of the digital value (i.e. logic `1` or logic `0`) which is to be applied to the input of the integrated circuit. Whereas, for the bits which correspond to the output pins of the integrated circuit, the value of the bit is representative of the digital value which is expected at the corresponding output of the integrated circuit.
The tester apparatus additionally includes a processor to control the application of the test vectors stored in the memory device to the integrated circuit. Each test vector is applied to the integrated circuit for a given time interval, which is largely dictated by the speed of the processor. The processor is coupled to both the integrated circuit socket and the ROM socket so that during each time interval the processor receives both the expected output pin values, as designated by the bits of the test vector set provided from the ROM, as well as the actual output pin values provided by the integrated circuit. In the event that a miscompare occurs between a bit value and a output pin value, the processor indicates that there is a fault within the integrated circuit device.
One technique for generating test sets involves identifying the functional blocks within the integrated circuit and generating subtests which exercise each identified functional block. Subtests are commonly generated through the use of computer simulation tools. A computer model of the integrated circuit is provided, and transactions which exercise the functional blocks of the integrated circuit are simulated. The signals which are provided to the input pins, and which appear at the output pins are "captured", that is their values at given time intervals are saved in a file for subsequent application to an actual integrated circuit during testing thereof.
One type of logic circuit commonly tested is a so-called synchronous logic circuit which has at least one reference signal generally referred to as a clock signal from which input signals and output signals are in general synchronized. While a synchronous logic integrated circuit may be simulated at any clock speed, the values of the input pins and output pins are usually "captured" at the midpoint of each half cycle of the clock signal, to ensure that the data which is captured is stable.
One drawback in the method of capturing the test vector at the midpoint of each half cycle of the clock signal in synchronous logic integrated circuits is that the captured vectors are already stable and thus the vectors do not reflect actual propagation delays and `setup` and `hold` conditions between and for the assertions of various signals.
TABLE 1 ______________________________________ ACTUAL DATA Time (ns) Clock Data ______________________________________ 0 0 0 6 0 1 10 1 1 30 0 1 44 0 0 50 1 0 ______________________________________
TABLE 2 ______________________________________ SAMPLED DATA Time (ns) Clock Data ______________________________________ 0 0 0 20 1 1 40 0 1 60 1 0 ______________________________________
By way of example, referring now to Table 1, a 50% duty cycle clock signal having a 40 nano-second (ns) period may be used to clock a flip flop (not shown) which is triggered by the rising edge of the clock signal. As shown in Table 1, the clock becomes asserted at 10 ns, remains asserted for 20 ns, (deasserting at time equal to 30 ns), and remains deasserted for the following 20 ns (asserting again at time equal 50 ns). A data signal which is to be received by the flip flop is provided so as to satisfy the setup and hold characteristics of the flip flop, by arriving a time period .tau. ns before the triggering edge of the clock, and remaining stable for at least a time period .lambda. ns after the triggering edge of the clock. For example, for the given flip flop .tau. may equal to 3 ns and .lambda. may equal to 2 ns. A data signal which would satisfy the setup and hold criteria for the flip flop is shown in Table 1 as becoming asserted at 6 ns, (4 ns before the clock becomes asserted), and remaining asserted until the 44 ns time interval, at which point the signal deasserts.
Referring now to Table 2, the sampled data obtained by using the above described technique of sampling the data and clock at the midpoint of each half-cycle of the clock period is shown. The result is a sampling of the clock and data signals at 20 nano-seconds (ns), 40 ns, and 60 (the midpoints between the 10 ns, 30 ns and 50 ns clock edges described with reference to Table 1).
When the signal values of Table 2 are used by the tester apparatus, it can be seen that at the 20 ns interval and the 60 ns interval the value of the clock pin and the value of the data pin change virtually simultaneously. If the clock pin and data pin both change in the same test vector on a test apparatus, either the set-up time or the hold time of the state device which receives the clock and data could be violated. Consequently, the input state devices of the integrated circuit being tested would not receive the correct data, and the output pins of the integrated circuit would therefore provide incorrect results. In such an instance, imperfect test vectors may cause a perfect integrated circuit to fail on the tester apparatus.
One technique used to avoid the above described situation is to ensure that during a simulation of the circuit that the clock pins and data pins always change in separate test vectors. This is accomplished by capturing a vector at the exact moment that one of the input data pins or the clock pin changes values during the simulation. Although this technique is effective, one problem with this technique is that it increases the number of test vectors that are produced, since not every data pin will change at the exact same instant. Large test sets are undesirable because the longer a test set is, the longer it takes to test the integrated circuit, and thus the testing period and hence cost for the integrated circuits is increased. An additional problem arises in that most testing apparatus can store only a fixed number of test vectors in the ROM. Therefore, it may not be possible to capture the vectors on every clock and data change and still have enough room in the ROM to completely test the integrated circuit.
A second type of logic circuit is a so called asynchronous logic integrated circuit. In general with these types of circuits outputs are related to present states of inputs without being synchronized by a reference signal. Often in these types of circuit it is important that signals change in a specified order or that the input signals do not change at the same time. Asynchronous logic circuits are also often tested by applying simulation generated data as generally mentioned above, and accordingly there is the associated problem in test set generation of providing a test set which correctly identifies a faulty asynchronous integrated circuit while utilizing as few test vectors as possible.